My notes on processor virtualization and Intel VT-x

+ Pacifica/AMD-V is present in every "AMD Athlon 64 with stepping "F" and "G", Athlon 64 X2 with stepping "F" and "G", Turion 64 X2, Opteron, Phenom, and all newer processors";

+ IVT/Intel VT exists as IA-32 VT-x (Vanderpool) and IA-64 VT-i (Silvervale);

+ Intel VT "is available on certain Pentium 4 6x1 and 6x2 models, Pentium D 9x0, Xeon 3xxx/5xxx/7xxx, Core Duo (excluding the T2300E and T2x50

models) and Core 2 Duo processors (excluding the T52x0, T5300, T54x0, T5500 with stepping "B2", E2xx0, E4x00 and E8190 models)";

+ VT-x adds root and non-root operation to IA-32;

+ In non-root operation processor operation is "changed substantially", as some instructions and events cause a "VM Exit";

+ The VM-execution control fields allow to specify the instructions and events that cause VM exits.

+ Instructions HLT, INVLPG, MOV CR8, MOV DR, MWAIT, RDPMC, and RDTSC (plus CR0, CR3, and CR4) can be trapped;

Excerpt:

For example, if the MOV CR instruction causes a VM exit, the exit reason would indicate “control-register access”; the exit qualification would indicate:

(1) the identity of the control register (for example, CR0);
(2) whether the MOV was to or from the control register; and
(3) which general-purpose register was the source or destination of the instruction.


+ VT-x and VT-i provide means for Address-Space Compression, Ring Aliasing/Compression, Nonfaulting Access to priveldged state, Guest system calls (SYSENTER, SYSEXIT) & Interrupt virtualization.

[...]

References:
http://softwarecommunity.intel.com/articles/eng/2722.htm
http://download.intel.com/technology/itj/2006/v10i3/v10_iss03.pdf
http://en.wikipedia.org/wiki/X86_virtualization